> > GORD: I almost certainly oppose silently allowing outputs to > > be unassociated. > > [SB] Verilog has always had implicitly unconnected module > ports, though. > Just omit them from the port connection list. Despite the syntactic similarities, I don't think it's right to decide what subprograms should or shouldn't do by appealing to what modules do. For example, we don't expect modules to act the same way as subprograms when their formals and actuals have differing vector widths. Personally, I would prefer to keep the rules as simple as possible, and forbid any defaults on anything other than inputs. I say that because there's still a little part of me that dreams of subprograms (or, at least, class methods) overloaded by argument signature; and I suspect that fancy defaults will interact in hard-to-predict ways with any future enhancements for overloading. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Tue Jul 17 04:52:53 2007
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