Re: [sv-bc] Confusion in function evaluation approach

Surya,

I believe that your approach 2 should be considered the correct one,
for two reasons.

1. It is the more useful and less surprising behavior.  Having the
evaluation of later arguments corrupt the earlier arguments is
undesirable and unexpected to users.

2. Verilog-XL behaves as in approach 2.  The standard was originally
based on the behavior of Verilog-XL, and this part of the standard
has not been deliberately changed.

It is easy for a naive implementation to behave as in approach 1.
NC-Verilog originally behaved this way.  Then this was reported as a
bug and was fixed.  Apparently some other implementations still have
this bug.  Cliff Cummings noticed this bug in some of those other
implementations when he was testing the Verilog-2001 support of various
tools, years ago.  He categorized it as a bug in recursive function
calls (which it isn't really, since the function is not calling itself).

Note that there can be other related bugs.  An implementation might
leave the return value of the first function call in the static reg
that holds the function return value, where it gets destroyed by the
second function call.  This is more likely to happen with very wide
vector values that don't fit into machine registers.

With SystemVerilog allowing functions to have output and inout args,
similar problems could occur on the output side also.

Steven Sharp
sharp@cadence.com


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