>From: "Alsop, Thomas R" <thomas.r.alsop@intel.com> >I also want to comment on a question I am seeing near Table 11-22 > > > >QUESTION: > >Is the shorter > >operand always > >zero extended, or > >can it be sign > >extended? > > > >It's referring to this sentence "If the lengths of the first and second >expression are different, the shorter operand shall be > >lengthened to match the longer and zero-filled from the left (the >high-order end)." This is more out-of-date text that was missed when signed arithmetic was added in Verilog-2001. Most of it has been tracked down and fixed, but not quite all of it. I think I may have entered a Mantis item for this one already. The operand should be zero-extended in an unsigned expression, and sign-extended in a signed expression. The sentence is over-simplistic in other ways as well. It does not acknowledge the possibility that the expression may have a context- determined size that is longer than either operand, requiring both operands to be lengthened, not just the shorter one. And it is written as if the two expressions are simple operands that will be lengthened immediately before the conditional operator. If they are more complex expressions with context-determined operands, then the lengthening will be performed on those operands to get the right length before reaching the conditional operator. This sentence is a poor substitute for the actual expression width rules that apply. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Aug 16 10:47:09 2007
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