[sv-bc] RE: [sv-ec] New proposal for Mantis 0001556: in-line static variable initialization - require keyword static?

Dave,

Why is the mandatory use of the keyword 'static' considered necessary?
Users are already free to add it to their code if their own coding
methodology requires it.  There's no ambiguity about the semantics of
static variables.  

Aren't users going to get confused by this rule?  They might guess that
omitting the required keyword would give them an automatic variable, but
instead they will get either an error message from a 2008 implementation
or a static variable from a 2005 implementation.

Old Verilog had many static variables with initializers and no 'static'
keyword, and, even after this change, in those contexts SV still won't
require the 'static' keyword for static variables with initializers.
What's so special about these new contexts where 'automatic' would also
be legal?  Why no requirement that 'automatic' be required for an
automatic variable with an initializer if it's in a context where
'static' would be legal?

The SV-EC have assured that the proposed change is backward compatible,
because in old Verilog there were no initializers for the variables in
static tasks and functions.  But that only means the change is backward
compatible with old Verilog.  

Surely there are at least a few existing SV designs that are legal in
IEEE Std 1800-2005 but that would suddenly become illegal after this
change?

   function static longint f(byte n);

      longint subtotal = 0;  // Illegal

      return (subtotal += n);

   endfunction

Don't get me wrong -- if it's progress, I'm for it.  I just don't see
yet why this change would be progress.

-- Brad


________________________________

From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Rich, Dave
Sent: Thursday, September 13, 2007 2:01 PM
To: sv-ec@eda-stds.org
Subject: [sv-ec] New proposal for Mantis 0001556: in-line static
variable initialization - require keyword static?



A new proposal has been uploaded with a new example. The example has
been split into two modules, one legal and the other illegal. All
implementation dependencies (race conditions) have been removed.

 

David Rich
Verification Technologist
Design Verification & Test Division
Mentor Graphics Corporation
dave_rich@mentor.com
Office:   408 487-7206
Cell:     510 589-2625

 


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