Re: [sv-bc] XMRs in parameter value overrides of module instantiations

>In parameter declarations, one can reference other
>*previously-declared* parameter values:
>     parameter p1 = 0;
>     parameter p2 = p1 + 5;
>but you can't swap the order of the declarations (nor make the
>defaults circular).

The requirement that the parameter be previously declared does
provide protection against circularity.  Allowing hierarchical
names in constant expressions creates a hole in that protection
(though unrestricted defparams do too).


>The Verilog-AMS committee has had some thoughts about having
>a "process constants" module that would contain, eg, TOX for
>both PMOS and NMOS, and the MOS modules would then use a
>hierarchical reference to obtain TOX, which would then allow it
>to be modified in one place to model process variation.

As Mark pointed out, SystemVerilog packages provide a mechanism
that allows this kind of thing cleanly.


Steven Sharp
sharp@cadence.com


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