[sv-bc] SVDB 1747 - NO-WAY !!!

At 01:16 AM 9/30/2007, Bresticker, Shalom wrote:
> > SVDB 1747 _x_Yes   ___No
> > http://www.eda.org/svdb/view.php?id=1747
>
>Responding to Cliff: this is one enhancement that many users want. We
>should honor their wishes.
>As for other objections, I would accept any other reasonable way to get
>the same effect.

With all due respect, I believe the requests have been skewed by 
misinformed engineers.

Most of the engineers who request this capability believe they will 
get the same declaration checks as VHDL. They will not.

When I explain to engineers that the additional required declarations:
(1)     do not check declaration sizes,
(2)     do not check connectivity,
(3)     can be easily defeated by making extra declarations,
(4)     require verbose declarations that could themselves introduce NEW bugs,

and that a better check would be to check connectivity, which does 
the following:
(1)     does not require additional declarations for all connections,
(2)     cannot be defeated by extra declarations,
(3)     helps find signals with no drivers,
(4)     helps find signals with no receivers,
(5)     helps find and eliminate extra dangling or forgotten declarations,
(6)     allows declaration of signals that are not yet connected 
(such as scan signals or unused bits of a declared port or internal bus)

then engineers quickly lose their interest in any form of the 
`default_nettype port_type wire proposal.

This proposal is nothing more that a band aid on another band aid. 
This proposal can help introduce as many errors as it fixes.

The real solution to this problem is to check connectivity as I 
proposed in August. If connectivity, which finds all of the same 
problems and more, is better served by linting tools (as suggested by 
the SV-BC in August), then this proposal, which only finds a small 
subset of the problems and misses many more problems including 
problems potentially introduced by the required declarations, should 
also be left to linting tools.

I can't believe we are considering this addition while discarding a 
far superior solution.

Try this - add both `default_nettype port_type wire AND connectivity 
checking and I promise you that engineers will overwhelmingly use 
connectivity checking and discard this half-baked solution. If we add 
both, I will vote yes (and then bad-mouth and shame anyone who uses 
this solution over connectivity checking).

Engineers request half-baked solutions when they don't know that a 
better solution could be proposed.

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


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