RE: [sv-bc] Mantis 1940

Hi Shalom,

 

Observe the following text from the proposal:

 

The net data types can represent physical connections between structural
entities, such as gates. A net shall not store a value (except for the
trireg net). Instead, its value shall be determined by the values of its
drivers, such as a continuous assignment or a gate. See Clause 10 and
Clause 27 for definitions of these constructs. If no driver is connected
to a net, its value shall be high-impedance (z) unless the net is a
trireg, in which case it shall hold the previously driven value.

 

The last sentence is a little bit troublesome.

 

First, if no driver is connected to a net, it is difficult to even

have a previously driven value.  The only way that is possible

seems to be via a force command.  Perhaps one could imagine

this text means that something like a bufif0 turned off its control

input?  But in that case, I'd still say there was a driver on the net,

but it is contributing a high-impedance (z) value.

 

Second, in either of those cases above, a trireg will hold a net at its

previous logic value, but the strength may change, depending what

the previously driven strength was.  Some people might read "value"

to mean "combination of logical value + strength".

 

I know this came from the existing LRM heritage.  But while you're at
it,

you might like to clean this up a little bit such that it's clearer and

more accurate.

 

One possibility would be to replace "value" with "logical value"

at the tail end of the sentence.  There surely are other improvements

to be made as well.

 

Thanks,

Doug

 

module top;

    trireg (medium) t1;

    trireg (medium) t2;

    trireg (medium) t3;

    trireg (medium) t4;

 

    reg ctl;

 

    bufif1 (weak0, weak1) (t1, 1'b1, ctl);

    bufif1 (strong0, strong1) (t2, 1'b1, ctl);

    bufif1 (pull0, pull1) (t3, 1'b1, ctl);

 

    initial begin

        $monitor("%2d: ctl=%0b t1=%v t2=%v t3=%v t4=%v", $time, ctl, t1,
t2, t3, t4);

        ctl = 1'b1;

        #10;

        ctl = 1'b0;

        force t4 = 1'b1;

        #10;

        ctl = 1'b1;

        release t4;

        #10;

    end

endmodule

 

From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org] On
Behalf Of Bresticker, Shalom
Sent: Tuesday, October 02, 2007 5:20 AM
To: sv-bc@server.eda.org
Subject: [sv-bc] Mantis 1940

 

<<1940_D3a.V3.htm>> 
Hi, 

I have prepared a new version of Mantis 1940. Please review. 

Thanks, 
Shalom 

Shalom Bresticker 
Intel Jerusalem LAD DA 
+972 2 589-6852 
+972 54 721-1033 

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