>From: Greg Jaxon <Greg.Jaxon@synopsys.com> >Yes. "Test" is either an inverter (if you read it as 1 downto 1) >or a buffer (if you read it as 1 upto 1). I think we should leave >this ambiguity in the language as a warning to future languages >on how NOT to declare arrays ;-) There are other places the blame could be placed, other than the way Verilog arrays are declared. The most obvious place would be the rule that +: and -: will automatically swap the left and right index to match the order in the declaration. That is what is breaking here, where the declaration has no order. If the starting bit were always the left index, and you used +: or -: depending on whether the range was ascending or descending (with reversed indexes still being an error), then this problem would not occur. Alternately, this problem can only occur with an out-of-range index. If any bits being out of range were treated as an out-of-range index, rather than trying to specially handle the in-range bits of a partially out-of-range index, then the problem would be avoided also. The index would be out-of-range. A read would produce x, and a write would have no effect, regardless of whether you considered the range to be ascending or descending. Steven Sharp sharp@cadence.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Oct 4 14:54:43 2007
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