Re: [sv-bc] Assignment operator in continuous assignment

Perhaps Surya's point is just that assign b = b + 1; is syntactically
legal.  If it is semantically repulsive enough that assign b += 1; isn't
syntactically legal, then maybe another error should be specified for
the first version, much as we're proposing to do for variable initializations.

Greg

Rich, Dave wrote:
> There is a difference in the way that a continuous assignment may be
> scheduled.
> 
> The procedural 'always @b b = b + 1;' is really two procedural
> statements: wait for an event on b, then increment b.
> 
> The continuous assignment 'assign b = b + 1;' says whenever there is an
> event in an operand on the RHS, evaluate the RHS, which could leaded to
> a zero-delay oscillation.
> 
> On the other hand, 'assign out = enable ? in : out ;' is OK because this
> combinatorial loop will settle out.
> 
> Dave
> 
> 
> 
>> -----Original Message-----
>> From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
>> Sent: Wednesday, October 10, 2007 1:02 AM
>> To: Rich, Dave; Surya Pratik Saha; sv-bc@server.eda.org; sv-
>> ec@server.eda.org
>> Subject: RE: [sv-bc] Assignment operator in continuous assignment
>>
>> It would have no effect.
>>
>> It would be like writing
>>
>> always @(b)
>> 	b = b + 1;
>>
>> That in itself would not be very useful.
>> But one could write
>>
>> assign b += c ;
>>
>> which would be like
>>
>> always @(b,c)
>> 	b = b + c ;
>>
>> which would trigger if c changed.
>>
>> Many years ago, we used to sometimes write latches as
>>
>> assign out = enable ? in : out ;
>>
>> But I don't think it is useful enough to recommend allowing it.
>>
>> Shalom
>>
>>> -----Original Message-----
>>> From: owner-sv-bc@server.eda.org
>>> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Rich, Dave
>>> Sent: Wednesday, October 10, 2007 9:45 AM
>>> To: Surya Pratik Saha; sv-bc@server.eda.org; sv-ec@server.eda.org
>>> Subject: RE: [sv-bc] Assignment operator in continuous assignment
>>>
>>> This is specifically disallowed. What would it mean in terms
>>> of sensitivity to have the same variable on both sides of '='?
>>>
>>> Dave
>>>
>>>
>>>> -----Original Message-----
>>>> From: owner-sv-bc@server.eda.org
> [mailto:owner-sv-bc@server.eda.org]
>>> On
>>>> Behalf Of Surya Pratik Saha
>>>> Sent: Wednesday, October 10, 2007 12:17 AM
>>>> To: sv-bc@server.eda.org; sv-ec@server.eda.org
>>>> Subject: [sv-bc] Assignment operator in continuous assignment
>>>>
>>>> Hi,
>>>> In SV 1800, continuous assignment syntax allows only '='
> assignment
>>>> operator. Why '+=', '-=' types of assignment operator not
>>> allowed. Why
>>>> someone can't write:
>>>>
>>>> assign b += 1;
>>>>
>>>> Which is just similar to
>>>> assign b = b + 1;
>>>>
>>>> Is there any specific reason or is it case of BNF overlook?
>>>>
>>>> --
>>>> Regards
>>>> Surya
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>> --
>>>> This message has been scanned for viruses and dangerous content by
>>>> MailScanner, and is believed to be clean.
>>>
>>> --
>>> This message has been scanned for viruses and
>>> dangerous content by MailScanner, and is
>>> believed to be clean.
>>>
>> ---------------------------------------------------------------------
>> Intel Israel (74) Limited
>>
>> This e-mail and any attachments may contain confidential material for
>> the sole use of the intended recipient(s). Any review or distribution
>> by others is strictly prohibited. If you are not the intended
>> recipient, please contact the sender and delete all copies.
> 


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.