RE: [sv-ac] Re: [sv-bc] Suppression of unique/priority glitches

 


> Consider the following (abusive situation):
>      initial begin
>        // assert something false  (1)
>        #0;
>        // assert something false  (2)
>        #1;
>        // assert something false  (3)
>     end

> In my approach, the process becomes active at time 0.  Any deferred
assertions (none) are flushed.  We then "schedule" assert 1 for the
observed region and do the #0.  The process becomes active *again* at
time 0.  Pending assertions -- i.e. assertion 1 -- are flushed.

If we are asserting something, then after an explicit #0 delay asserting
something else, why should the first assertion be considered a glitch?
Isn't it likely that these are two different checks of two different
conditions?

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