RE: [sv-bc] E-mail Ballot: Respond by Oct 14, 2007 8am PDT

Cliff wrote on Mantis 1464:

SVDB 1464 No

As long as we are making corrections to the example, the "assumed to be
instantiated"
module is also wrong because the matching internal bus declarations are
also required.

I would vote yes if the proposed change is modified as follows:

TO

The following example demonstrates the usage of extern module
declarations.

extern module m (a,b,c,d);
extern module a #(parameter size= 8, parameter type TP = logic [7:0])
(input [size:0] a, output TP b);

module top ();
wire [8:0] a;
logic [7:0] b;
wire c, d;
m mm (.*);
a aa (.*);
endmodule

Modules m and a are then assumed to be instantiated as follows:

module top ();
wire [8:0] a;
logic [7:0] b;
m mm (a,b,c,d);
a aa (a,b);
endmodule 


[SB] I agree and will make that change.

Shalom
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