RE: [sv-bc] E-mail Ballot: Respond by Oct 14, 2007 8am PDT

Let me step back to something more basic.

In Verilog, if I have

module m;
integer i;
initial
	for (i=0; i<16;i=i+1) begin:a
		reg r ;
	end
endmodule

Then r has a hierarchical name of m.a.r, correct?

If in SV, I write

module m;
initial
	for (int i=0; i<16;i=i+1) begin:a
		reg r ;
	end
endmodule

Can I hierarchically reference r? If so, what is its hierarchical name?

Thanks,
Shalom
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