RE: [sv-bc] SVDB 1619 Examples

Cliff,

Again, the cases are not similar. No one argues with you about today. Of
course, DC does not implement 1800-2008 today. Five years ago, it did
not implement SV either. And in 2001, it did not implement 1364-2001
either.

In pipe2.v, you have 

  logic        pu1 = 1'b1;

That is like

  logic        pu1;
  initial 
	pu1 = 1'b1; 

and initial procedures are not synthesized.

In pipe3.v, "a 1619 equivalent", you have 

  input        d, clk, rst_n, rst2_n='1);

But it is not equivalent. rst2_n in this case has a default port
connection value. I think maybe now I am beginning to understand your
difficulty. 

1619 does not propose something like a port pullup. What is a pullup? In
a pullup, you have a fixed internal driver to '1. When the port is
driven from outside, it overrides the pullup as long as the drive is
strong enough. If the driver from outside stops driving, the pullup is
felt.

1619 is different. It is just a shorthand for writing port connections.
It means that in a port connection, if you wrote

pipe3 pipe3 ( ..., .rst2_n(cucu), ...) ;

then rst2_n is connected to cucu, and the '1 does not exist. If cucu is
not driving, i.e., it is 'z, then that is what rst2_n gets. However, if
you omitted rst2_n from the list of connections, then it would be as if
you had written 

pipe3 pipe3 ( ..., .rst2_n('1), ...) ; 

This latter is certainly synthesizable.

Regards,
Shalom

> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Clifford E. Cummings
> Sent: Monday, October 15, 2007 1:23 AM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] SVDB 1619 Examples
> 
> Hi, All -
> 
> Attached is a tar-file with three 2-flop pipeline models.
> 
> pipe1.v has reset going to the second flop but not the first. 
> Synthesizes fine.
> pipe2.v has different resets going to the different flops. 
> The first flop reset is internally tied through a continuous 
> assignment to a variable initialized in the declaration (the 
> closest I can get to
> 1619 with current coding styles) while the second reset comes 
> in through a port. Try synthesizing that model and tell me 
> what you get (I used DC and warnings about ignored 
> initializations and both flops disappear).
> pipe3.v is the 1619 proposed equivalent to pipe2.v
> 
> This is why I am concerned.
> 
> Regards - Cliff
> 
> At 12:44 PM 10/14/2007, Jonathan Bromley wrote:
> >Re. 1619 (defaults on module inputs):  Cliff said
> >
> > > If Synopsys supports this in synthesis, then other tools could be 
> > > shamed into supporting this feature.
> >
> >I fear the boot is somewhat on the other foot.  For some 
> time Synopsys 
> >DC was the only synth tool I know about that didn't 
> correctly support 
> >VHDL's default inputs on modules (it accepted the syntax, 
> but defaulted 
> >the inputs to zero regardless of the specified value); it's fine 
> >nowadays, though.
> >All the FPGA-oriented tools have supported VHDL default inputs 
> >correctly since forever.  This is old, well-cooked technology.
> >
> > > There are other synthesis tools, like Synplicity, that ignore 
> > > initial blocks and hence initial assignments
> >
> >Surely the default is a constant_expression, and so no 
> "initial" block 
> >is implied or needed?
> >--
> >Jonathan Bromley, Consultant
> >
> >DOULOS - Developing Design Know-how
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> >
> >Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, 
> Hampshire, BH24 1AW, UK
> >Tel: +44 (0)1425 471223                   Email: 
> jonathan.bromley@doulos.com
> >Fax: +44 (0)1425 471573                           Web: 
> http://www.doulos.com
> >
> >The contents of this message may contain personal views 
> which are not 
> >the views of Doulos Ltd., unless specifically stated.
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com Expert 
> Verilog, SystemVerilog, Synthesis and Verification Training
> 
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