Hi, All - Much to my surprise, my SVDB login is not working so I cannot enter proposals to meet today's deadline. Let me at least list the topics with a commitment to make entries when (if) my login is restored (when you are a trouble maker, they take away your login :-) ) Not all of these can become ready for the 2008 standard but i will get them entered and work on them ASAP. Regards - Cliff 1800-2008 To-Do Proposal List initialx, alwaysx, always_combx, always_latchx, always_ffx Proposal: To address x-optimism and x-pessimism simulation issues. Synthesis tools would treat these keywords exactly like the non-x version of the keywords. ----- 2-state reproducible random initialization - Needs donation of HP patent - probably will not be ready for p1800-2008 vote but it should be tracked ----- extend covergroups - Users complain that covergroups cannot be extended. Would it be possible to extend covergroups that are declared in classes? ----- Cliff to add Mantis item for 15.10 - clocking block clarification ----- continue(label) - (safe, restricted goto replacement) within the same procedural block scope. This would facilitate implicit FSM creation by adding an argument to the continue command. By restricting the jump to a labeled item in the same procedural block scope, there should be no problem with spaghetti code-like goto statements ----- wire () ... declarations - simulators shall completely ignore the () in these declarations. This syntax can facilitate testing for illegal connectivity in a design. Could help enable -dangles Proposal in a future version of the standard. ----- wire-reg-logic proposal - SystemVerilog allows single continuous assignments to declared variables, add othogonality to SystemVerilog and allow procedural assignments to net types. Just like with variables, first-use determines if the assignment behaves like a continuous assignment or a procedural assignment and it shall be illegal to make both assignment-types to a net. ----- unique0 (parallel_case) - there is a need for a parallel_case equivalent. Propose adding the keyword unique0. ----- final-block $strobe warning - issue a warning if a final block encounters a $strobe command ($strobe commands in final blocks are legal but never execute). If a final block encounters a $strobe command, then the simulator shall produce a runtime warning to indicate that the $strobe command is ignored by a final block. ----- Enhancement request from Japanese engineer - increment enumerated types by a defined step amount. The engineer noted that they had an enumerated type with over 1500 enumerated names that each had to increment by 4 after making the initial assignment. The engineer asked for the syntax: typedef enum step 4 bit [15:0] { // <-- define the enum increment with 4 step // B_SAMPLE B_A_SAMPLE_SOFTWARE_RESET = B_A_BASE_SAMPLE, B_A_SAMPLE_CLOCK_ENABLE, B_A_SAMPLE_POWERSAVE_DISABLE, ... } B_A_t; Perhaps a different syntax could be proposed if this one is not acceptable. ----- Fix attributes - V2K attributes are almost worthless in their current incarnation. Change them to be more text based. ----- Define timing for disable statements that disable code with nonblocking assignments and RHS delays The behavior of the disable statement has long been ambiguous and silent regarding nonblocking assignments and future nonblocking assignments. Some simulators disable future events defined within the disabled scope while others only disable events in the current time region of a time slot. This inconsistency has led to some authors discouraging ALL use of the disable statement. ----- `default_nettype var-type compiler directive At first blush this might look confusing, but really it is not. For all practical purposes, a `default_nettype declaration would have been better named as `default_type. I believe it would be more confusing to now add a second default-type directive such as `default_vartype, because we would run into precedence issues between the default-types and odd situations when one was changed but the other was not. ----- <<= assignment operator: Selectable nonblocking assignment that behaves either like <= for 0-delay high-speed regression runs or like <= #1 for debug and waveform-display simulation. ----- Clarify the .name implicit ports require unconnected ports to be listed in the instantiation. ----- UDP event scheduling - Sequential UDPs (any UDP with a reg declaration) should behave like nonblocking assignments and make updates to the UDP output in the NBA Region (some simulators do this while others make the updates in the Active Region). ----- Signed Arithmetic Operators - signed arithmetic in Verilog is mostly broken. There is no such thing as a signed data type in real hardware, only signed operators. Add true HDL signed operators (operators surrounded by angle brackets) with optional arguments to reference standard ieee arithmetic operations: <+> <-> <*> </> <**> <*, ieee754float> </, ieee754float> This may not be doable for this version of the standard, but I would like to see it entered and considered. ----- An ARM engineer has reported problems with case (...) inside using 2-state variables. Proposal to potentially address the problem. ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon Oct 15 07:05:21 2007
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