Re: [sv-bc] confusion in determining the type of an self determined binary expression during evalution of type operator

>From: Greg Jaxon <Greg.Jaxon@synopsys.com>

>> I would say that you need to normalize only if the types of then- and
>> else- expressions do not match. If the types are matching (or "same"),
>> it would be more useful to let the conditional operator return this
>> type, rather than to artificially normalize it. This is especially true
>> for non-integral types.
>
>Especially true for enum types (which shouldn't reduce to integers here).

While this may seem reasonable at first glance, a closer look shows that
they do reduce to integral values here, and need to.

The LRM says "An enum variable or identifier used as part of an expression
is automatically cast to the base type of the enum declaration."  So it
is clear that they do reduce to integers here.  There are reasons why
they need to.

The then- and else- expressions are context-determined operands, so
their type is determined by the type of the expression they appear
in, regardless of whether they match each other or not.  Since they
may have their signedness changed and their width extended before
the conditional operator is even applied, clearly the result does not
have the enum type.
   
You may have only been thinking about the case where the conditional
appears in a self-determined context or as the RHS of an assignment.
But even there it doesn't work.

You are assuming that the result of the conditional will always be the
value of one of the two operands.  But this is not true in Verilog.
The condition can be unknown, in which case the result is computed by
combining the bit patterns of the other two operands.  That result may
not be a valid value for the enum type (and probably isn't, since any
non-matching bits will come out X).  If the result were treated as
if it were of the enum type, then you have broken the protection that
was supposed to be provided by the enum type rules.

Steven Sharp
sharp@cadence.com


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