Re: [sv-ac] RE: [sv-bc] Suppression of unique/priority glitches

From: Gordon Vreugdenhil <gordonv_at_.....>
Date: Tue Oct 16 2007 - 13:58:30 PDT
<grin>

Steven and I answered "no" and "yes" respectively on the
original combined questions but we are agreeing -- it
does NOT constitute a rescheduling so it DOES preserve
assert2/assert1 combination as I detailed in my prior mail.

Gord.

Steven Sharp wrote:
>> From: "Seligman, Erik" <erik.seligman@intel.com>
> 
>> So here's a question for the gurus:  does reaching the 'end' and going
>> back to the 'begin' constitute a rescheduling?
> 
> No.  It is just a jump to the top, like the end of a forever or for-loop.
> 
> Steven Sharp
> sharp@cadence.com
> 
> 

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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Received on Tue Oct 16 13:58:50 2007

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