RE: [sv-bc] RE: [sv-ec] That modport direction issue again

 

> From: Gordon Vreugdenhil 
>
> My current preference is that the LRM should explicitly
> exclude assignments through virtual interfaces as being
> part of the "single driver" determination.  Since such
> constructs are not synthesizable, if a design satisfies
> the "single driver"  invariants without considering
> the virtual interface aspects, I believe that the end
> result will be Ok.

When simulation tools are just enforcing synthesis
single driver rules, it makes sense to exclude test bench
constructs like virtual interfaces. 

This is, however, something that is likely to cause problems
for users. The simulator is using a last writer wins
resolution function, which may lead to unexpected behavior
that will surprise users. 

Since it is very expensive and a lot of overhead to do the
single driver rule through virtual interfaces at run time,
it makes sense to exclude it for efficiency reasons, but when
possible I think we should not be adding blanket waivers of 
the single driver rule for all test bench constructs.

> 
> I do have a related question however.
> 
> Is there any deeper assumption about modport directions
> than there is for ports?
> 
> I believe the answer is "no" based on various comments
> but I want to make sure that we're all on the same page.
> 
> In particular, in Mark's full example, if you change
>      modport MP (output L);
> to
>      modport MP (input L);
> 
> Is there any impact at all?

If you only change the modport direction in that example, then
there is at least one simulator that will give and error because
both modules m and m2 are writing to an input port, but I am not
sure this is what you are asking about.
 
> I have always assumed that there isn't but we have had
> users asking about this.
> 
> As with module ports and as the example in 24.5.4 explicitly
> indicates, "input" ports can be associated with constants
> and the like while "output", etc. cannot.  But those are
> just basic port semantics and I am assuming that nothing
> more strict applies.

I think module are not allowed to write to variable input ports.
I'm not sure what other semantics you are thinking of.

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