Re: [sv-bc] New Proposal uploaded for Mantis 2005

Hello all;

Section 16.4.4, the last example could be enhanced to show the 
connection between the signals
used in the assertion and the signal being registered. Presumably the 
connection is to show
that 'a' or 'b' is influenced (changed) by state being changed.

module fsm(input clk, rst, a, b);
...
always_comb begin : b1
    a42: assert @(posedge clk) (a == b);
    ...
end
always_ff (@posedge clk) begin : b2
    state = nextstate; // change to a or b ?
    ...
end
endmodule

I have a concern with this close syntax and quite different operation.

good:   assert property ( @(posedge clk) a == b);
almost: assert @(posedge clk) (a == b);

The assertion labeled 'good' is a concurrent assertion that will verify 
'a' versus 'b'.
The assertion labeled 'almost' is a deferred assertion that will NOT 
result in any assertion report
if 'a' or 'b' are registers based on 'clk'.  And yet it almost looks 
correct - even to the trained eye.

Could it be one of these syntaxes to more correctly distinguish between 
the two ? The #0
better distinguishes concurrent assertions from deferred assertions.

better1: assert #0 @(posedge clk) (a == b);
better2: assert @(posedge clk) #0 (a == b);



Warmke, Doug wrote:
> Hi SV-AC,
>
> I finally got our ideas incorporated into Erik's proposal,
> and I uploaded it to Mantis.  The "Motivation" section
> includes discussion of various changes (features and
> non-features) that were made.  Hopefully that will
> forestall later attempts to re-introduce them.
> (I did forget to add an explanation of why non-zero
> delay_control values would be a bad idea, but that
> can be added later).
>
> See http://www.eda-stds.org/svdb/view.php?id=2005
> and look at the attached file SV-2005_D4-1.pdf.
>
> Tej will be available to explain the proposal and answer
> questions during the regular SV-AC meeting.
>
> By the way, I created a similar proposal for unique/priority
> if/case (Mantis 2008).  Pending review of 2005, I can modify
> the proposal for 2008 and then upload it to Mantis as well.
>
> Regards,
> Doug
>
>   

-- 
    Soli Deo Gloria
    Adam Krolnik
    Director of Design Verification
    VeriSilicon Inc.
    Plano TX. 75074
    Co-author "Assertion-Based Design", "Creating Assertion-Based IP"


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