Re: [sv-bc] Re: if-else

>From: John Havlicek <john.havlicek@freescale.com>

>- In "expresson != 0", the constant 0 is signed 32-bit.  Are there
>  any cases in which we should use 1'b0 instead of 0?

The equivalence should not be taken too literally.  The expression is
still self-determined.  Neither its evaluation width nor signedness
is affected by the pretend zero.  If you want something more precise,
it would have to be (expression != 1'sb0), to avoid affecting the
width or signedness.

>- Are there any cases where "expression" has no bit at all?  If so,
>  is sign-extension defined?  I am worried about void members of 
>  tagged unions and similar things.  Perhaps a tagged union with 
>  only one member and such that the one member is void type.

There were no such cases in Verilog.  If I had noticed any cases being
added in SV, I would have raised issues with them.  I didn't notice
void members of tagged unions.  

There are no rules for how to treat void values in an expression.  A
void function call in an expression would be illegal.  Therefore, I
would have to conclude that a reference to a void member of a tagged
union is not a legal expression, and cannot be used in one.  A tagged
union with only one member (and thus no need for a tag), and the one
member being void, would also need to be dealt with.  I would conclude
that either its declaration is illegal in the first place, or a reference
to the union as a whole is still considered a void value and is not an
expression.  Alternately, a void could be considered an expression but
not of integral type, and therefore unusable in an integral expression.

Thanks for pointing out this possible issue.  I don't think you need to
worry about it for your particular area, since it is a more general
problem that needs to be resolved for all cases.

Steven Sharp
sharp@cadence.com


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