RE: [sv-ac] Re: [sv-bc] Re: if-else

I don't think you need special semantics for if-else, 1'b0 will work, as
well as '0. The LRM already says this about the equality operator

If the operands are of unequal bit lengths and if one or both operands
are unsigned, the smaller operand shall be zero-extended to the size of
the larger operand. If both operands are signed, the smaller operand
shall be sign-extended to the size of the larger operand.

> -----Original Message-----
> From: owner-sv-bc@server.eda.org [mailto:owner-sv-bc@server.eda.org]
On
> Behalf Of Steven Sharp
> Sent: Thursday, November 01, 2007 11:42 AM
> To: Eduard.Cerny@synopsys.com; john.havlicek@freescale.com
> Cc: john.havlicek@freescale.com; sharp@cadence.com;
sv-ac@server.eda.org;
> sv-bc@server.eda.org
> Subject: Re: [sv-ac] Re: [sv-bc] Re: if-else
> 
> 
> >'b0 is another possibility.  I am trying to understand the
> >technical distinction, if any, from the different choices.
> 
> If you actually had (expression != 'b0), that would force the
> expression to be evaluated at a width of 32 bits (if it were
> itself narrower) and unsigned.  But again, this is taking the
> equivalence too literally.  The semantics of "if (expression)"
> are those of self-determined evaluation of expression, followed
> by a comparison of that value with a zero of equivalent width
> to the result, or more simply, a check for any 1 bits.
> 
> Steven Sharp
> sharp@cadence.com
> 
> 
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