Re: [sv-bc] void in an actual expression?

Steven Sharp wrote:
> void members of tagged unions being used in an expression
>  Opinions?

Begin by accepting that void is a packed integral type with 0 bits.

Making void packed allows it be used to make "union tagged packed" objects
without violating the rule that packed objects cannot contain unpacked
fields.

Void should be understood to be "signed" for the purposes of
typing the surrounding expression.  This does the least harm to
the type of expressions in which it may appear.

Sign extension of a void shifts in 1'bX.  This is consistent with
the access to its sign bit, which being out-of-range should return
an X.   Unsigned extension does the same thing, just as it would
for 1'bX.

If it were legal to use the C-style bounds declaration for packed
dimensions, and legal to supply the value 0:

void nil;   // would be equivalent to:
logic signed [0] nil;

The behavior of 0-extension on such data types would have to be noted
as a special case, as it is already special-cased for X and Z.

In this point of view, "void", joins "byte" and "integer" as just another
predefined vector length.  We have some weak impediments to adding
packed dimensions of these types, but they can be finessed; unpacked
dimensions are not a problem, however.  So we should expect an almost
unbounded number of distinct void-based types of different shapes (but all
the same size, of course).

Greg Jaxon

P.S. Obligatory Empty Array Joke:
 Son:  Pop, I saved a quarter today: I missed the bus and ran after it instead.
 Dad:  Next time run after a taxi and save $3.50.





> 
> 
>>> - Are there any cases where "expression" has no bit at all?  If so,
>>>  is sign-extension defined?  I am worried about void members of 
>>>  tagged unions and similar things.  Perhaps a tagged union with 
>>>  only one member and such that the one member is void type.
>> There were no such cases in Verilog.  If I had noticed any cases being
>> added in SV, I would have raised issues with them.  I didn't notice
>> void members of tagged unions.  
>>
>> There are no rules for how to treat void values in an expression.  A
>> void function call in an expression would be illegal.  Therefore, I
>> would have to conclude that a reference to a void member of a tagged
>> union is not a legal expression, and cannot be used in one.  A tagged
>> union with only one member (and thus no need for a tag), and the one
>> member being void, would also need to be dealt with.  I would conclude
>> that either its declaration is illegal in the first place, or a reference
>> to the union as a whole is still considered a void value and is not an
>> expression.  Alternately, a void could be considered an expression but
>> not of integral type, and therefore unusable in an integral expression.
> 
> 
> Steven Sharp
> sharp@cadence.com
> 
> 


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