RE: [sv-ac] Re: [sv-bc] Re: if-else

You seem to have a different interpretation of what a correct
implementation should be. :)

I think you are incorrectly determining that the result of the
arithmetic shift should be unsigned. That would be true in the case of
an arithmetic or relational operation, but not in the case of equality.
Equality has its own explicit rules for dealing with signedness.

Dave


> -----Original Message-----
> From: Steven Sharp [mailto:sharp@cadence.com]
> Sent: Thursday, November 01, 2007 2:48 PM
> To: sharp@cadence.com; Eduard.Cerny@synopsys.com;
> john.havlicek@freescale.com; Arturo.Salz@synopsys.com; Rich, Dave
> Cc: sv-ac@eda.org; sv-bc@eda.org
> Subject: RE: [sv-ac] Re: [sv-bc] Re: if-else
> 
> 
> >From: "Rich, Dave" <Dave_Rich@mentor.com>
> 
> >Has anyone come up with a case where 1'b0 would not work? What about
'0?
> 
> You mean for the "equivalent" comparison?  Sure:
> 
> module top;
> initial
> begin
>   if (1'sb1>>>1)
>         $display("expression true");
>   if ((1'sb1>>>1) != 1'b0)
>         $display("(expression != 1'b0) true");
>   if ((1'sb1>>>1) != '0)
>         $display("(expression != '0) true");
>   if ((1'sb1>>>1) != 1'sb0)
>         $display("(expression != 1'sb0) true");
> end
> endmodule
> 
> In a correct implementation, this prints
> 
> expression true
> (expression != 1'sb0) true
> 
> and none of the others.  Using an unsigned zero gives incorrect
results.
> 
> Steven Sharp
> sharp@cadence.com


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