RE: [sv-bc] RE: [sv-ac] sampled assertion function vs data types - refereing to prior simulation

>From: "Jonathan Bromley" <jonathan.bromley@doulos.com>

>> > Maybe someone in SV-BC can clarify.  The question is, given 
>> > the declarations below is the initial value of w 1'bz or 1'bx?
>> > 
>> >   reg r;
>> >   wire w;
>> >   assign w = r;
>
>[the initial value of w]
>> Should be 1'bx.
>> Since r is unitialized, it is 1'bx.
>> w is driven by r.
>
>1'bx even in the Preponed region of the very first timeslot???
>Surely the first activation of the continuous assignment
>cannot occur until the Active region of time 0?
>Or is this too mechanistic a view of continuous assignment?

It is not too mechanistic a view of continuous assignment.  However,
it is too mechanistic a view of the initial value of a wire.  These
are not physical wires that will naturally float at z until a driver
starts driving them (and we can't really say much about what is
supposedly happening before time 0 anyway, and whether the driver is
really not driving before time 0).

A simulated wire will start with whatever value the simulator initializes
it to before the simulation starts.  The first time its drivers are
evaluated, that result will be propagated to it.  I would interpret that
statement about wires assuming the value of their drivers as being a
requirement that continuous assignments must be evaluated at time zero,
even though none of their inputs may have changed.  Otherwise a continuous
assignment of 1'b0 to a net would never get propagated, because there is
no change in its value to trigger its evaluation.

So what value will a simulated wire start with?  I think it would be
dangerous to count on a specific value, as this may differ between
implementations.  As long as they manage to get the correct value
propagated to the wire during the first time slot, they have not had
to worry about what the value would be in the Preponed region of that
time slot.

I can tell you that NC-Verilog does the reverse of the suggestion of
starting at z and then transitioning to x at time zero if driven.  It
starts all nets at x and transitions them to z at time zero if not
driven.  This x->z transition creates an event that ensures that things
like pass gates will be evaluated and propagate the z through to the
other side (which would otherwise remain x).  A continuous assignment
that drives something non-x at time zero (like a constant 1'b0) will
be evaluated and update the net to that value.  That x->0 transition
will cause an event that will activate any fanout to evaluate and
propagate any effects.

So the answer in NC-Verilog will be x.  But I don't think you can count
on that being the answer in other implementations.

Steven Sharp
sharp@cadence.com


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