Hi, All - Attached is my example that shows my concern regarding default port values. I still think it is dangerous to use the enhanced models with the SV .* implicit port connections that added much stronger checking on instantiated models. I will probably be the lone no-vote on 1619 for this reason. Regards - Cliff ---------------------------------------------------- Cliff Cummings - Sunburst Design, Inc. 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005 Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and Verification Training -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.
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