RE: [sv-bc] E-mail Ballot: Respond by 8AM PST, Mon, Dec 10, 2007

 I am going to send out the proposal to describe the way import works.
The write up is an attempted formalization of name when wild card
imports
are present.
I want to try to fix a couple of things that Gordon pointed out but if 
I cannot get to it tonight, I will send what I have anyways.

Francoise
    '


-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
Gordon Vreugdenhil
Sent: Friday, December 07, 2007 7:16 PM
To: Clifford E. Cummings
Cc: sv-bc@eda.org
Subject: Re: [sv-bc] E-mail Ballot: Respond by 8AM PST, Mon, Dec 10,
2007


On 1809, the answer to your additional red and "does it cause an error"
is "yes it does".  The first reference does a definite import even
though that isn't what "f"
eventually resolves to; the later named import is an error.

I agree with Francoise that this is perhaps not ideal although there are
some odd effects (particularly in $unit) in any solution.  One's
expectations can be at odds with any approach.

That said, I've done a couple of detailed reviews of something Francoise
is working on that would handle imports in a less eager manner.  I'm not
completely sold on it, but it definitely is worth talking about.
Hopefully that will come out publicly before Monday.

Gord.


Clifford E. Cummings wrote:
> Summary of Cliff's votes. See attached file for questions.
> 
> Regards - Cliff
> 
> SVDB 1339  Yes
> SVDB 1345  Yes
> SVDB 1583  Yes - Question
> SVDB 1809  No
> SVDB 2222  Yes
> SVDB 2225  Yes  - Question
> 
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486 cliffc@sunburst-design.com / 
> www.sunburst-design.com Expert Verilog, SystemVerilog, Synthesis and 
> Verification Training
> 

--
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Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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