[sv-bc] E-mail Ballot Due Dec 17 8AM PST

Here are my votes.

Francoise
    '

SVDB 1397 _ X __Yes   ___No 
http://www.eda.org/svdb/view.php?id=1397

SVDB 1809 ___Yes   ___No 
http://www.eda.org/svdb/view.php?id=1809
I prefer the proposal I made. I am against eager import binding
from proposal #1.


SVDB 2037 ___Yes   _X__No 
http://www.eda.org/svdb/view.php?id=2037
Because configurations are not part of the Verilog source, I am
uncomfortable
making anything else other than literals be assigned to parameters.

SVDB 2106 _X__Yes   ___No 
http://www.eda-stds.org/sv-bc/hm/7701.html
http://www.eda.org/svdb/view.php?id=2106

SVDB 1602 _X__Yes   ___No 
http://www.eda.org/svdb/view.php?id=1602  

SVDB 2097 _X__Yes   ___No 
http://www.eda.org/svdb/view.php?id=2097 


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