[sv-bc] RE: [sv-ec] Task/Function ANSI style declaration with non-ANSI port

That's Mantis issue 1169

    http://www.eda-stds.org/svdb/view.php?id=1169 

which was ETF issue 227

    http://www.boyd.com/1364_btf/report/full_pr/227.html

-- Brad


-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of
Surya Pratik Saha
Sent: Sunday, December 16, 2007 9:36 PM
To: sv-ec@eda.org; sv-bc@eda.org
Subject: [sv-ec] Task/Function ANSI style declaration with non-ANSI port

Hi,
For non-ANSI style port declaration of task/function, we know a port can
be declared with a direction first, then it can declared with its data
type. So following case is legal.

task mytask;
  input d;
  reg d;
endtask

Now is it possible to declare the port with direction in ANSI style, but
explicit data declaration later. Here is the e.g.:
task mytask (input d);
  reg d;
endtask

As per Verilog 1364-2005 LRM it is mentioned for ANSI style module port
declaration that ANSI style port declaration should be complete. I am
not sure whether it is applicable to task/function also, as LRM is
silent on that. Most of the tools however passes the case. Can someone
comment on that?

-- 
Regards
Surya





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