Actually hierarchical identifiers are allowed in parameter overrides in module instantiation statements. See Manti 1058 and 1224. Shalom > -----Original Message----- > From: Steven Sharp [mailto:sharp@cadence.com] > > >SVDB 2037 ___Yes _X_No > >http://www.eda.org/svdb/view.php?id=2037 > > I am concerned that a hierarchical identifier is allowed in > an override. > There are reasons why hierarchical identifiers are not > allowed in overrides (whether on an instance or a defparam) > in the Verilog source: it can lead to circularities. It > appears to me that the same issue arises here. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sun Dec 16 23:09:50 2007
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