[sv-bc] FW: E-mail Ballot Due Dec 17 8AM PST

>-----Original Message-----
>From: Steven Sharp [mailto:sharp@cadence.com] 
>Sent: Monday, December 17, 2007 9:03 AM
>Subject: Re: E-mail Ballot Due Dec 17 8AM PST
>
>
>>From: Don Mills <mills@lcdm-eng.com>
>
>
>>>I am concerned that a hierarchical identifier is allowed in 
>an override.
>>>There are reasons why hierarchical identifiers are not 
>allowed in overrides
>>>(whether on an instance or a defparam) in the Verilog 
>source: it can lead
>>>to circularities.  It appears to me that the same issue arises here.
>>
>>
>>Shalom has addressed this.
>
>I don't agree that a mistake accidentally allowed into the 
>language in one
>place is a justification for deliberately allowing it again.
>
>>If a built-in system function is used, it is evaluated at 
>elaboration and that 
>>value is passed to the parameter, the same as a literal would 
>be passed.  If 
>>PLI modifies the built-in system function later-on then the 
>parameter does not 
>>see the modification.
>
>I don't see anything in the LRM that suggests that a 
>user-defined override
>of a built-in system function does not apply at elaboration 
>time.  It would
>be very irregular for the same syntax to mean two different 
>things in the
>same design, depending on whether it is in an elaboration-time constant
>expression.
>
>Steven Sharp
>sharp@cadence.com
>
>

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