Re: [sv-bc] Mantis 1984

Brad Pierce wrote:
> Following up to 
> 
>    http://www.eda-stds.org/sv-bc/hm/7774.html
> 
> In the following example, only the first assignment is legal?
> 
> 
> module test(input logic A, input logic B, input var C, D );
>   assign A = 0;  // legal
>   always @* begin
>       B = A ;    // illegal to procedurally assign to wire
>       C = A ;    // illegal to assign to input variable

I agree, but the reason that it is illegal is due to the
procedural/continuous conflict on "C".  An "input" variable
port is assumed to have a continuous driver on it; that is
the reason that the procedural assignment is illegal.  The
continuous assignment to "D" (the next assignment) is
illegal since that means there are multiple continuous
assignments on "D" -- the assumed one on the high side
and the explicit one in the module.

It would, for example, be perfectly legal to "force"
any of the vars even though they are inputs since "force"
does not count as either procedural or continuous in
terms of the driver considerations.

Gord.


>   end
>   assign D = 0;  // illegal to assign to input variable
> endmodule
> 
> 
> -- Brad
> 
> 

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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