The other important aspect is my assertion that a "force" to an input var port is NOT illegal. Reading the second sentence in isolation implies that a force would not be legal and I would object to that interpretation. Gord. Bresticker, Shalom wrote: > I think you are both correct. > > I think there is an implicit "Therefore, ", i.e., > > "A continuous assignment shall be implied when a variable is connected > to an input port declaration. [Therefore,] assignments to variables > declared as an input port shall be illegal." > > What the added sentence does is cover the case where the input port is > unconnected. Some people might have considered that case ambiguous. > > Shalom > > >> -----Original Message----- >> From: owner-sv-bc@server.eda.org >> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Brad Pierce >> Sent: Friday, January 04, 2008 3:01 AM >> To: sv-bc@server.eda.org >> Subject: RE: [sv-bc] Mantis 1984 >> >> According to 22.3.3.2 (draft 4) -- >> >> "Assignments to variables declared as an input port shall >> be illegal." >> >> Isn't that sufficient to make the assignment to C illegal? >> >> -- Brad >> >> -----Original Message----- >> From: Gordon Vreugdenhil [mailto:gordonv@model.com] >> Sent: Thursday, January 03, 2008 4:44 PM >> To: Brad Pierce >> Cc: sv-bc@eda.org >> Subject: Re: [sv-bc] Mantis 1984 >> >> >> >> Brad Pierce wrote: >>> Following up to >>> >>> http://www.eda-stds.org/sv-bc/hm/7774.html >>> >>> In the following example, only the first assignment is legal? >>> >>> >>> module test(input logic A, input logic B, input var C, D ); >>> assign A = 0; // legal >>> always @* begin >>> B = A ; // illegal to procedurally assign to wire >>> C = A ; // illegal to assign to input variable >> I agree, but the reason that it is illegal is due to the >> procedural/continuous conflict on "C". An "input" variable port is >> assumed to have a continuous driver on it; that is the reason that the >> procedural assignment is illegal. The continuous assignment >> to "D" (the >> next assignment) is illegal since that means there are multiple >> continuous assignments on "D" -- the assumed one on the high side and >> the explicit one in the module. >> >> It would, for example, be perfectly legal to "force" >> any of the vars even though they are inputs since "force" >> does not count as either procedural or continuous in terms of >> the driver >> considerations. >> >> Gord. >> >> >>> end >>> assign D = 0; // illegal to assign to input variable endmodule >>> >>> >>> -- Brad >>> >>> >> -- >> -------------------------------------------------------------------- >> Gordon Vreugdenhil 503-685-0808 >> Model Technology (Mentor Graphics) gordonv@model.com >> >> >> -- >> This message has been scanned for viruses and >> dangerous content by MailScanner, and is >> believed to be clean. >> >> >> > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > > -- -------------------------------------------------------------------- Gordon Vreugdenhil 503-685-0808 Model Technology (Mentor Graphics) gordonv@model.com -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Jan 4 08:58:35 2008
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