RE: [sv-bc] `include

Shalom,
     I noticed this in my review of the compiler directives section earlier.  At the time, I did not yet have a Mantis account to create an entry for this.
 
 I have just created Mantis 2251 for this issue.
 I will upload a proposed resolution sometime this week based on what I had suggested here:
 http://www.eda-stds.org/sv-bc/hm/5982.html
Once I get my new wording into the proper format to be uploaded.
 
~Alex

________________________________

From: owner-sv-bc@server.eda.org on behalf of Bresticker, Shalom
Sent: Sat 1/26/2008 11:05 PM
To: sv-bc
Subject: [sv-bc] `include



Hi, 

The following is a merge issue, already noted by the editor, but not yet dealt with by us. 
There are other merge issues, but this one is particularly prominent: 


21.4 contains the following text: 

The filename is the name of the file to be included in the source file. The filename can be a full or relative 
path name. 

The filename can be enclosed in either quotes or angle brackets, which affects how a tool searches for the 
file. 

- When the filename is enclosed in double quotes ("filename"), the behavior of `include is 
unchanged from Verilog. 
- When the filename is enclosed in angle brackets (<filename>), then only the vendor-defined location 
containing files defined by the language standard is searched. Relative path names given inside the 
angle brackets are interpreted relative to the vendor-defined location in all cases. 

When the filename is an absolute path, only that filename is included and only the double quote form of the 
`include can be used. 

The text, "the behavior ... is unchanged from Verilog," is not appropriate for the merged LRM. 

Shalom 


-- 
This message has been scanned for viruses and 
dangerous content by MailScanner <http://www.mailscanner.info/> , and is 
believed to be clean. 

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.