[sv-bc] types for "inside" operands

Earlier discussions regarding the semantics for "inside" with
respect to reals implies that typing of expressions in an
"inside" is similar to a complex conditional.  So, for example,
consider the following:
     reg signed [3:0] r = 1;
     reg [3:0] r2;
     ...
        if (r inside [ -1 : r2 ]) ...

If this is equivalent to:
     r >= -1 && r <= r2
then the condition is false for all values of r2 since the
unsignedness of "r2" contaminates the entire condition and
all comparisons are done as 32 bit unsigned comparisons.  So
-1 is a very large unsigned 32 bit value and the range is empty
for any value of r2 (since it is width extended in an unsigned
manner).

In the context of a "case (...) inside", I further assume that
the type of all expressions (terms of each set and the case
expression) have their types unified prior to any comparisons
being done.

I think this is consistent with Steven's comments in Mantis 1805
but want to make sure that this matches everyone's expectations
since, once again, the Verilog semantics here can be very surprising
to users.

Gord.
-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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