Re: [sv-bc] sign/width casting semantics

Here's a puzzle:  write a macro that increments the value of its packed vector
expression argument without changing the type of that expression in any way.

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`define INCR(N) ((N) + signed'(1'b1))

This is the thing that Shalom thinks should not work.
It is an expression I have needed again and again in Verilog.
If you can write it for me some better way, I will concede
this whole point.

Greg











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