FW: [sv-bc] sign/width casting semantics

 

-----Original Message-----
From: Bresticker, Shalom 
Sent: Friday, February 01, 2008 10:08 AM
To: 'Greg Jaxon'; 'sv-bc'
Subject: RE: [sv-bc] sign/width casting semantics

type(N)'(N+1) ?

See 6.23.

Shalom 

> -----Original Message-----
> From: owner-sv-bc@server.eda.org
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Greg Jaxon
> Sent: Wednesday, January 30, 2008 9:10 PM
> To: 'sv-bc'
> Subject: Re: [sv-bc] sign/width casting semantics
> 
> Here's a puzzle:  write a macro that increments the value of its 
> packed vector expression argument without changing the type of that 
> expression in any way.
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> `define INCR(N) ((N) + signed'(1'b1))
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> This is the thing that Shalom thinks should not work.
> It is an expression I have needed again and again in Verilog.
> If you can write it for me some better way, I will concede this whole 
> point.
> 
> Greg
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