[sv-bc] Does `\'" violate V95 compatibility?

In Verilog it is legal to
`define \`"  42
You'd invoke this using `\`" , but according to P1800-2008 draft 4:

A `\`" indicates that the expansion should include the escape sequence \".

Modifying their example slightly:
    `define msg(x,y) `"x: `\`" y`\`" `"
An example of using this `msg macro is:
    $display(`msg(left side,right side));
The example above expands to:
    $display("left side: \" right side\" ");

But under V95 it would have expanded to either:
    $display("left side: 42right side42");    or
    $display("left side: 42 right side 42 ");   depending on how token gluing was treated.

I don't think it's a serious violation.
Is there a list of these nits?

Greg Jaxon



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