RE: [sv-bc] What will be the evaluated expression?

From: Subhamoy Pal <spal_at_.....>
Date: Mon Mar 10 2008 - 01:47:13 PDT
Thanks Very much for correcting me.

Subhamoy

-----Original Message-----
From: Gordon Vreugdenhil [mailto:gordonv@model.com] 
Sent: Monday, March 10, 2008 2:13 PM
To: Subhamoy Pal
Cc: sv-bc@eda.org; sv-ec@eda.org
Subject: Re: [sv-bc] What will be the evaluated expression?

Subhamoy, you missed applying one of the rules that you quoted:

    Perform sign extension if and only if the operand type
    (after type coercion) is signed.
    ^^^^^^^^^^^^^^^^^^^^^

Due to the presence of unsigned terms (i.e. "sel"), the overall
expression type is unsigned so unsigned extension is applied.
The "unsigned" aspect of the overall type is determined before
you do the extension.

Gord


Subhamoy Pal wrote:
> What will be the evaluated value of the expression (in red) for the 
> following testcase?
> 
>  
> 
> module test508(in1, in2, sel, out1);
> 
>    input in1, in2;
> 
>    input [5:0] sel;
> 
>    output reg  out1;
> 
>  
> 
>    always @(in1 or in2 or sel)
> 
>    begin
> 
>        case(sel)
> 
>            4'sh1a: out1 = in2;
> 
>            default: out1 = in1 ;
> 
>        endcase
> 
>    end
> 
> endmodule
> 
>  
> 
>  From LRM 1364-2001, it looks like,
> 
> *4.5.2 Steps for evaluating an expression*
> 
> - Determine the expression size based upon the standard rules of 
> expression size determination.
> 
> - Determine the sign of the expression using the rules outlined in
4.5.1.
> 
> - Coerce the type of each operand of the expression (excepting those 
> which are self-determined) to the
> 
> type of the expression.
> 
> IEEE
> 
> HARDWARE DESCRIPTION LANGUAGE Std 1364-2001
> 
> Copyright (c) 2001 IEEE. All rights reserved. 63
> 
> - Extend the size of each operand (excepting those which are 
> self-determined) to the size of the
> 
> expression. Perform sign extension if and only if the operand type 
> (after type coercion) is signed.
> 
>  
> 
>  
> 
> For this expression - size is 4 (Table 29 in LRM 1364-2001), it is 
> signed. Hence the evaluated value in binary becomes - 4'b1010.
Extending 
> the value with the size of 'sel' (size 6), it becomes 6'b111010
(signed 
> extension). But contradictory to that most of the simulators treat it
as 
> 6'b001010. Why is so?
> 
>  
> 
> Are the tools not doing it correctly or am I missing anything?
> 
>  
> 
> Your response is important for me.
> 
>  
> 
> Thanks in advance,
> 
> Subhamoy
> 
> 
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-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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Received on Mon Mar 10 01:49:22 2008

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