[sv-bc] Re: [sv-ec] [Fwd: Notes from meeting w/ Dmitry and SV-BC and SV-EC members]

From: Gordon Vreugdenhil <gordonv_at_.....>
Date: Mon Mar 10 2008 - 23:47:23 PDT
Tom, thanks for taking great notes on the meeting.

Thomas Thatcher wrote:
> 
[...]
>    Dave:  Would not be able to use automatic variable for part select.
>       e.g. for (int i=0; i<3; i++) assert property (@clk a[i:i+2])
>    Mark: Many people against putting assertions into loops.  Have to be
> be careful of the hierarchical naming.
>    Dmitry: Current proposal was developed with a lot of help from Gord

One quick note on this just to make sure that people understand
where I am on this.

I really do not like checkers in loops either.  Originally when
I raised substantive objections, no one else was speaking up so
I assumed that everyone accepted the base semantics and worked with AC
members on moving the description away from a "rewrite this into
a generate" approach to the current from which at least has many
fewer problems in terms of name conflicts, etc.  No one should construe
my work on this as support for the underlying approach of having checkers
in loops.

Gord
-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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Received on Mon Mar 10 23:49:19 2008

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