[sv-bc] Usage of named event

Hi,
Verilog 1364-2005 LRM introduces the named event declaration. Section 
9.7.3 mentions where an event can be allowed. But it is not mentioned 
usage of other places is illegal. Consider the following e.g.:

module top;
event line_end_event;
initial
begin
  
   if (line_end_event)   // --> is it an error?
    begin
    end
   wait(line_end_event);  // --> is it an error?
end

endmodule

SV allows 'null' to be assigned to named event. Considering that fact, 
wrt SV, is the case legal, because 'if (line_end_event)' can be read as 
'if (line_end_event != null)'.

-- 
Regards
Surya





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