Re: [sv-bc] realtime is by default signed or unsigned.

>From: Dhiraj Kumar Prasad <dhiraj@cal.interrasystems.com>

>Consider the following example.
>
>module tmp();
>logic signed [63:0] var1 [1:0];
>realtime var2[1:0];
>
>initial
>var2 = var1;
>
>endmodule

I believe that the LRM requires that the array elements to have equivalent
types for the arrays to be assignment compatible.  However, some people
have found the wording confusing, and may have concluded something different.


>For above testcase some simulator is showing error as "Array elements 
>must both be signed or both be unsigned" while
>some is passing.

I think in the first case, the simulator is discovering that the element
types are not equivalent.  It is producing an error, as it should, but
the message is incorrect about the reason.  I suspect that if you change
var1 to unsigned, it will still give you an error.  It may even give you
the same message, because it may work by treating reals as having a
signedness that is different from signed or unsigned.

In the second case, the implementation(s) may have been based on a
different understanding of the assignment compatibility rules for arrays.
They may have implemented an inefficient array assignment that performs
conversions on each element during assignment.  Alternately, they may
just have failed to detect the error, and will produce some kind of
garbage from the array assignment.

>So I was in confusion that whether is should be treated as signed or 
>unsigned.

It is signed, but that is not relevant to this array assignment testcase.
A real is not is not equivalent to any integral type, signed or unsigned.

Steven Sharp
sharp@cadence.com


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