[sv-bc] data types

Hi,

6.3 says,

"Several SystemVerilog data types are 4-state types, which can store all
four logic values. All bits of 4-state vectors can be independently set
to one of the four basic values. Some SystemVerilog data types
are 2-state, and only store 0 or 1 values in each bit of a vector. Other
exceptions are the event type
(see 6.17), which has no storage, and the real types (see 6.12)."

Except for the sentence about 2-state types, this text basically comes
from 1364.

But event types now do have some storage, and there are other data
types, such as class and chandle.

Suggestions for rewording?

Thanks,
Shalom

Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6582
+972 54 721-1033

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