[sv-bc] bit (part) select indexed by variable net connected to output

IEEE 1364 disallows to connect to ouput, inout below items:

Variables
- Expressions other than the following:
- A scalar net
- A vector net
- A constant bit-select of a vector net
- A part-select of a vector net
- A concatenation of the expressions listed above

SV defines new rules for net and vars - but there is no word about bit
(part) select. Maybe bit/part selects should be also be mentioned and proper
restriction defined (if exists).

19.12.1 Port connection rules for variables

- An output port can be connected to a variable (or a concatenation) of a
compatible data type. A continuous assignment shall be implied when a
variable is connected the output port of an instance. Procedural or
continuous assignments to a variable connected to the output port of an
instance shall be illegal.
- An output port can be connected to a net (or a concatenation) of a
compatible data type. In this case, multiple drivers shall be permitted on
the net as in Verilog.19.12.2 Port connection rules for nets

19.12.2 Port connection rules for nets

- An output can be connected to a net or variable (or a concatenation of
nets or variables) of a compatibledata type.
- An inout can be connected to a net (or a concatenation of nets) of a
compatible data type or left unconnected, but cannot be connected to a
variable.

 

Example:

module top;
    parameter p=1;
    int index;
    wire [3:0] w;
    reg [3:0] r;


    sub uut1(r[p]); //allowed
    sub uut2(w[p]);//allowed
    sub uut3(r[i]);//???????
    sub uut4(w[i]);//?????????

    sub uut1(r[p+:2]); //allowed
    sub uut2(w[p+:2]);//allowed
    sub uut3(r[i+:2]);//???????
    sub uut4(w[i+:2]);//?????????


endmodule


module sub (output o); //module sub (inout io);

endmodule

 

DANiel


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