[sv-bc] svlog enum function usage

Hi,

 

System Verilog provides some enum functions(section 4.10) like: next,
prev, last, first etc. for use. I have a doubt whether the following
statement (highlighted) is valid:

 

module test(input clk, input in, output out);

 

typedef enum {red, yellow, blue, green} color;

color my_color

 

always @(clk)

begin

 

my_color = blue;

my_color = my_color.prev.next.next

 

end

endmodule

 

i.e. are stacked up function calls valid? SVlog LRM does not mention
anything about this, so it would be great to have some feedback on this.

 

Thanks,

Kapil


-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.