Hello, Array of instance unrolling for port connection of array having both packed and unpacked dimensions is valid or not?. SV LRM 1800-2005 does not say anything regarding this mixed case. So my query is whether following testcase is valid or not? module top ; wire [3:0]A[0:1][0:1][0:1]; leaf l1[0:7] (A); endmodule module leaf(input wire [1:0]B[0:1]); endmodule Some standard simulators show errors for this above testcase and some don't. Thanks and regards, Moumita -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Mon May 5 00:38:25 2008
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