RE: [sv-bc] merge error on timescale

In Draft 5, 3.13.2.3 says,

"It shall be an error if some design elements have a time unit and
precision specified and others do not." 

Shalom


> -----Original Message-----
> From: owner-sv-bc@server.eda.org 
> [mailto:owner-sv-bc@server.eda.org] On Behalf Of Steven Sharp
> Sent: Thursday, May 29, 2008 7:28 PM
> To: sv-bc@server.eda.org
> Subject: [sv-bc] merge error on timescale
> 
> IEEE Std 1364-2005 19.8 specifies "It shall be an error if 
> some modules have a `timescale specified and others do not."
> 
> An equivalent statement does not appear in draft 5 of the merged LRM.
> I do not see a Mantis item with a proposal for removing this 
> requirement, therefore it should appear.
> 
> I expect that the requirement needs to be modified somewhat 
> for SV.  There are now other mechanisms for setting the 
> timescale, so it should say something like "have a timescale 
> specified" instead of "have a `timescale specified".  Also, 
> there are now design elements other than modules, and the 
> requirement should apply equally to them.  The compilation 
> unit poses particular problems, since `timescale apparently 
> doesn't apply to it, only the newer mechanisms.  It is also 
> unclear whether it always exists, or only exists if something 
> is declared in it.
> 
> Steven Sharp
> sharp@cadence.com
> 
> 
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