[sv-bc] package contents

Hi,

25.2 contains three different lists of what packages may contain. None
of the three are complete. Each is different from the others. Three
different lists within the same subclause seems redundant and confusing.
I would think that one would be enough, with a few additional words to
indicate that the list is not complete.

These are the three lists:

"SystemVerilog packages provide an additional mechanism for sharing
parameters, data, type, task, function, sequence, and property
declarations among multiple SystemVerilog modules, interfaces, and
programs."

"Types, nets, variables, tasks, functions, sequences, and properties may
be declared within a package."

"Items within packages are generally type definitions, tasks, and
functions...It is also possible to populate packages with parameters,
variables, and nets."

and this is the BNF, which formally defines the complete list:

package_item ::=
	package_or_generate_item_declaration
	| anonymous_program
	| package_export_declaration
	| timeunits_declaration

package_or_generate_item_declaration ::=
	net_declaration
	| data_declaration
	| task_declaration
	| function_declaration
	| dpi_import_export
	| extern_constraint_declaration
	| class_declaration
	| class_constructor_declaration
	| local_parameter_declaration ;
	| parameter_declaration ;
	| covergroup_declaration
	| overload_declaration
	| concurrent_assertion_item_declaration
	| ;

Shalom

Shalom Bresticker
Intel Jerusalem LAD DA
+972 2 589-6582
+972 54 721-1033

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