[sv-bc] RE: [sv-ec] out of bounds bit-select in vlog

I agree.
BTW, your "vect[0:+5]" should have been "vect[0:+6]".
 
Shalom


________________________________

	From: owner-sv-ec@server.eda.org
[mailto:owner-sv-ec@server.eda.org] On Behalf Of Kapil Kaushik
	Sent: Tuesday, June 03, 2008 10:21 AM
	To: sv-bc@server.eda.org; sv-ec@server.eda.org;
sv-ac@server.eda-stds.org
	Subject: [sv-ec] out of bounds bit-select in vlog
	
	

	Hi,

	 

	Verilog 2001 section 4.2.1 mentions the following:

	 

	If the part-select is out of the address bounds or the
part-select is x or z, then the

	value returned by the reference shall be x.

	 

	Now for the following case:

	Vect[4:0];

	my_vect = vect[5:0]; 

	Or 

	my_vect = vect[0+: 5]

	 

	(where my_vect is [5:0])

	 

	Does this imply that my_vect[5] = x or my_vect[5:0] = x (i.e.
all bits are 'x')? 

	 

	Although I feel that the former should be true, but just wanted
to confirm the same, because if reference here refers to the whole
vector, then the whole vector will be x.

	 

	Also, in case this is true, then if my_vect be [6:0], the msb
bits must be auto extended by x (as verilog LRM says), right?

	 

	Thanks,

	Kapil


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