[sv-bc] Query regarding clocking block signals

Hi,

According to LRM IEEE Std 1800-2005 Section 15.2 :

"All input or inout signals specified in the clocking block are sampled 
when the
corresponding clock event occurs. Likewise, *all output or inout signals 
in the
clocking block are driven when the corresponding clock event occurs*. 
Bidirectional
signals (inout) are sampled as well as driven. *An output signal cannot 
be read*, and
an input signal can-not be driven."

module top(input clk,input reg[3:0] in1, output reg[3:0] out1);

assign out1 = in1;

clocking clkB @ (posedge clk);
 input in1;
 output out1;
endclocking

endmodule

Is the testcase given above valid?

Some standard simulators are passing this testcase while some others are
giving the following error message:

"out1' is driven procedurally and continuously"

Thanks,
Sarani



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