[sv-bc] Scope specific keyword

Hi,
Does SV or Verilog LRM define some keywords as scope specific? I did not 
see any. But some of the standard simulators considers 'instance' as 
keyword inside 'config' scope only. In other places, you can use it as 
identifier. Though Verilog 1364-2005 LRM defines 'instance' in the 
keyword list. So following case should fail:

module top;
    integer instance;
endmodule

Please let me know it is the simulator bug or am I missing anything.

-- 
Regards
Surya




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