RE: [sv-bc] Query on multiply instantiated modules...

This is the correct behavior.
See IEEE Std 1364-2005, subclause 7.1.6:
The terminal connections for an array of instances shall follow these
rules:

- The bit length of each port expression in the declared instance-array
shall be compared with the bit length of each single-instance port or
terminal in the instantiated module or primitive.

- For each port or terminal where the bit length of the instance-array
port expression is the same as the bit length of the single-instance
port, the instance-array port expression shall be connected to each
single-instance port.

 
Shalom


________________________________

	From: owner-sv-bc@server.eda.org
[mailto:owner-sv-bc@server.eda.org] On Behalf Of Anand Gurusamy
	Sent: Tuesday, August 05, 2008 12:24 PM
	To: sv-bc@server.eda.org
	Cc: Kapil Kaushik
	Subject: [sv-bc] Query on multiply instantiated modules...
	
	

	Hi there,

	 

	In the top level design "top", module "mid" is instantiated as
below.

	- - - - output logic dout;

	- - - - mid i_mid [1:0] (

	            .state_o(dout),

	            -

	            -

	            -

	            -

	);

	 

	The above module is elaborated as,

	mid \i_mid[0]  (

	    .state_o(dout), 

	      -

	      -

	      -

	      -

	);

	 

	mid \i_mid[1]  (

	    .state_o(dout),

	      -

	      -

	      -

	      -

	);

	 

	After elaboration, it looks like the signal "dout" is multiply
driven (from the output "state_o" of both the instantiations).

	Would this be the correct behavior?

	Or since "dout" is one bit, should some kind of truncation take
place and only the output "state_o" of module "\i_mid[0]" be connected
to dout?

	 

	Please let me know incase if there are any pointers on this in
the LRM.

	 

	Thanks

	-Anand

	 


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